In many counting, timing and similar operations, it is often necessary to detect a particular count state of a counter on which is predicated the activation of some event. For example, to generate accurately a time delay function, a typical method is to count in a counter regularly occurring pulses and to detect a particular count state, such as "all zero", in the stages of the counter. The pulse rate and the number of count states between the beginning and detected count states determine the length of the time interval generated.
In instances in which large counts are involved, it is often desirble to use polynomial counters. A polynomial counter is one in which the logic state assumed by an initial stage of the counter responsive to each pulse to be counted is jointly determined by the then existing logic states of at least two other prescribed stages of the counter. The logic states assumed by the remaining stages of the counter responsive to each counted pulse is simply the state of the immediately preceding stage. Because of these attributes, polynomial counters are usually implemented by shift registers and the count states through which a polynomial counter progresses as pulses are counted do not form a binary progression in the base 2 numerical system as is the case with, for example, ripple counters.
It is desirable to use such shift register polynomial counters where the number of counter stages is large because of the ease and economy of fabrication of shift registers by integrated circuit techniques. Generally, such counters require about half the number of circuit elements as conventional flip-flop counters.
It is relatively easy to determine when a desired count state has occurred when ripple or other types of counters are used which have overflow, or carry, outputs. Typically, a recycling counter is used which has precisely the number of count states required to measure or generate the desired function. A recycling counter is one which automatically returns to its beginning count state in the process of counting pulses after it has progressed through all of its count states. When the counter recycles, an overflow, or carry signal, is generated and used as an indication of the attainment of the desired count state. This technique is not applicable to polynomial counters, however, because of the lack of an overflow signal. The inability to provide an overflow signal in a polynomial counter is caused by the fact that the state of each successive stage of the counter, except the initial stage, is determined only by the immediately preceding stage, as will be seen.
In other instances, a desired count state is detected by examining all stages of a counter for the appropriate logic states which together define the desired count. This technique, however, although applicable to counters having any type of state progression, becomes increasingly cumbersome and expensive as the number of counter stages increases. This is because of the additional circuitry required to decode the logic state of each of the counter stages. Indeed, in counters involving sufficiently large numbers of stages, the additional decoding circuitry may become the dominant portion of the overall circuit.